The disclosure relates to a method for manufacturing a semiconductor device and, more particularly, to a method for forming an analog capacitor and a cell capacitor simultaneously without an additional process.
An excellent way to increase competitiveness in the semiconductor manufacturing industry is decreasing chip size by inducing a technology for fabricating fine structure in order to increase chip number per wafer, and at the same time increasing a production yield. In a dynamic random access memory (DRAM), these benefits may be obtained, but capacitance required by the DRAM unit cell is fixed, so to obtain adequate capacitance, the surface area of a cell capacitor may be secured.
As the size of the semiconductor device is minimized, two methods are introduced to secure cell capacitance. First, the height of the cell capacitor is extended to increase the surface area thereof. Second, a dielectric layer of the cell capacitor is formed of selected materials having high dielectric constant. A Ta2O5 layer and/or a BST((Ba,Sr)TiO3) layer replace(s) a nitride layer, which is usually used as a dielectric layer.
Requirements, of the system on chip (SOC) structure have been strongly raised due to its various advantages. In particular, a technology realizing a memory device, such as DRAM, and a logic device within one chip is required, so merged DRAM with logic (MDL) and embedded DRAM with logic (EDL), etc. have been developed. Most logic circuits comprise an analog circuit and, especially, general usage of an analog capacitor has gradually been realized.
There have been numerous attempts to obtain capacitance required in the MDL. For example, the height of the capacitor may be extended, and hemispherical grains (HSG) may be formed on a surface of the charge storage electrode to increase the surface area of the capacitor. Also, electrodes of a capacitor may be formed with proper materials in order that the dielectric layer of the capacitor is formed with materials having high dielectric constants. In the case of Ta2O5, a metal insulator silicon (MIS) structure may be adopted, and in the case of other dielectric materials, such as BST, a metal insulator metal (MIM) structure may be adopted to form a capacitor.
In the tendency of manufacturing process to increase cell capacitance in the MDL, a cell capacitor having the MIM structure may be formed in a memory cell region, and an analog capacitor, of which electrodes and a dielectric layer are different from the cell capacitor, may be formed in a logic circuit region.
However, in such a process, the process complexity is increased because the cell capacitor and the analog capacitor are separately realized. Also, as the height of the cell capacitor is increased, the depth of the contact hole is consequently increased, and it is difficult to completely fill the contact hole.
Therefore, difficulties of manufacturing may be increased and lowering of reliability may occur. Moreover, Pt and Ru, which are representative materials for a capacitor electrode of a next generation DRAM, are expensive, so the materials may be effectively used, but in a conventional case, a cell capacitor and a logic capacitor are separately formed so that it is difficult to expect the effective usage of the materials.
FIGS. 1A to 1H are cross-sectional views illustrating a conventional semiconductor manufacturing process.
Referring to FIG. 1A, a well (not shown) and an isolation layer 13 of each of a cell region A and a logic region B are formed on a substrate 11, and a gate electrode 14 and a gate hard mask 15 are then formed on the substrate 11. The gate electrode 14 is formed from a polysilicon, a tungsten silicide, tungsten, or a combination thereof, and the gate hard mask 15 is formed of an oxide layer, a nitride layer, or a combination thereof. At this time, a logic gate is simultaneously formed in the logic region B. The logic gate has a polycide/capping layer structure and in some cases, the capping layer may be omitted.
Subsequently, a source/drain is formed using an ion injection method, etc., and a sidewall spacer 17 is formed on the gate electrode 14 and the gate hard mask 15. Concentrations of the source/drain of the cell region A and the logic region B may be different from one another. Also, a salicide process is carried out to decrease a resistance of the source/drain 16 and a contact to be formed. The sidewall spacer 17 is formed of an oxygen layer, a nitride layer, or a combination thereof.
An interlayer insulating layer 18 is formed on the resulting structure including the gate hard mask 15, and the interlayer insulating layer 18 is planarized.
Referring to FIG. 1B, a plurality of first plugs 19 of a cell region A, for example, a contact plug for storage node is formed using a polysilicon or a tungsten material, and an interlayer insulating layer 20 is deposited. Next, a bit line contact hole 21 is formed in a cell region A by selectively etching the interlayer insulating layer 20, and in a logic region B, a contact hole 22, which exposes the gate electrode 14 of the MOS transistor or the source/drain connection 16, and a metal wiring contact hole are formed.
Referring to FIG. 1C, plugs are subsequently formed, each of which is filled into the contact holes 21 and 22, respectively, for example, a bit line contact plug 23 and a MOS contact plug 24, and a bit line 25 is formed in a cell region A using a tungsten or a tungsten silicide material. Subsequently, metal wiring 26 is formed in the logic region B.
Interlayer insulating layers 27 and 28 are formed on an upper portion of the resulting structure of the bit line 25 and the metal wiring 26. In FIG. 1C, the interlayer insulating layer 27 for preventing oxidation and increasing adhesion of the bit line 25, may be omitted.
Referring to FIG. 1D, the interlayer insulating layers 27 and 28 of the cell region A are selectively etched to formed a contact hole, which exposes a surface of the first plug 19, and a second plug 29 is formed using a conductive material. The double plug forming technology is followed by a process to increase cell capacitance by increasing the height of a cell capacitor according to size minimization of the pattern.
Referring to FIG. 1E, an etching stopping layer 30 and an interlayer insulating layer 31 are successively deposited on the resulting structure including the second plug 29 and an interlayer insulating layer, and an opening portion within which a bottom electrode may be formed is formed by selectively etching an interlayer insulating layer of the cell region A and an etching stopping layer 30. The etching stopping layer 30 is used as a masking layer in a wet etching process, so according to the selected wet etchant, the used materials are changed; a nitride layer type of material is usually used.
A conductive layer is deposited on a bottom and side portions of the opening portion, and on the interlayer insulating layer 31 using materials for a bottom electrode, such as a polysilicon and tungsten materials. Subsequently, an interlayer insulating layer 33 for covering a conductive layer of bottom and side parts of the opening portion is formed, i.e., by forming the insulating layer on the resulting structure and removing it using an etch back to leave the insulting layer within the opening portion, and carrying out a chemical mechanical polishing (CMP) process with respect to a surface of the interlayer insulating layer 28 to form a bottom electrode 32. The insulating layer 33 prevents etching of a conductive layer forming the bottom electrode 32, and is formed with the SOG or an oxide layer, which is used in forming a field oxide layer.
Referring to FIG. 1F, the bottom electrode 32 is exposed by selectively removing the interlayer insulating layer 31 on the cell region A and an insulating layer, then forming a dielectric layer 34 and a top electrode 35. The dielectric layer 34 is usually formed with an oxide layer-type and a Ta2O5 layer.
Referring to FIG. 1G, the interlayer insulating layers 36 and 37 are deposited on an upper portion of a resulting structure including the top electrode 35, and metal wirings 39 and 40 are formed in the cell region A and the logic region B, respectively, by repeating an etching and depositing and an etching process, then in the logic region B, a bottom electrode 38 of a logic capacitor is formed. The bottom electrode 38 of the analog capacitor is formed with aluminum and/or a tungsten material.
A dielectric layer is deposited using an oxide layer, a nitride layer, or combination thereof, and a conductive layer, such as a TiN layer, is deposited, then a dielectric layer 41 of a logic capacitor and a top electrode 42 pattern are formed by etching the conductive layer and the dielectric layer. In this process, the dielectric layer is etched and removed in an outside region of an analog capacitor.
Next, referring to FIG. 1H, a post-process, such as forming interlayer insulating layers 43 and 45, and forming a metal wiring 44, is performed.
However, the conventional manufacturing process has the following problems.
First, when forming an electrode for a digital capacitor in the cell region A, the electrode material is deposited on the whole substrate and in a patterning process, and the electrode material deposited on a logic region is removed. Also, in forming a logic capacitor, an electrode material deposited on the cell region A may be removed. Therefore, due to a cost burden due to electrode material (precious metal) waste, a forming process of a cell capacitor may be performed with the MIS and/or the SIS structure, so processing is complicated, and because of process minimization, storage capacity reaches a limit.
Also, metal wiring is formed after completing the DRAM cell process, a contact hole depth of a contact hole is deepened, and the process to fill the depth is difficult. This problem is more serious if a pattern is minimized to a great extent.
Another problem is in forming an analog capacitor between metal wirings in a semiconductor device, such as in an MDL, i.e., the number of processes is increased and planarization of an interlayer insulating layer is difficult due to the increasing height experienced in forming an analog capacitor.
A technology used to form a cell region and a logic region is disclosed in U.S. Pat. No. 6,143,601, as follows.
Referring to FIG. 2A, a well and a separating layer 53 of a cell region A and a logic region B, respectively, are formed on a substrate, and patterned after depositing a gate electrode 54 and a gate hard mask 55. The gate electrode is formed with materials such as a polysilicon, a tungsten silicide, tungsten, or combination thereof, and the gate hard mask 55 is formed with an oxide layer, a nitride layer or combinations thereof.
Next, a source/drain connection 56 is formed using an ion injection method, and a sidewall spacer 57 is formed in the gate electrode 54 and the gate hard mask 55. In forming a source/drain connection 56, a concentration of the source/drain connection in a cell region A may be different from that of the source/drain connection in a logic region B. A salicide process may be adapted to decrease resistance of the source/drain connection 56 and post-contact resistance. Meanwhile, the sidewall spacer 57 is formed with an oxide layer, a nitride layer and a combination thereof.
Subsequently, an interlayer insulating layer 58 is formed on a resulting structure including the gate hard mask 55, and a planarization process is carried out. At this time, a logic gate is simultaneously formed. The logic gate has a polycide/capping structure, and the capping layer formation may be omitted.
A plug 59 and wiring 60 forming process is carried out to form a bit line contact/bit line in the cell region A, and metal wiring in the logic region B, that is, a local wiring contact/local wiring, simultaneously.
Referring to FIG. 2B, after depositing an interlayer insulating layer 61, an etching stopping layer 62 is formed using a nitride layer for a dual damascene process, and by patterning the etching stopping layer 62, a contact region, for example, in case of a cell region, a storage node contact, and in case of a logic region, a metal wiring contact are defined. Next, an interlayer insulating layer 63 is formed on the etching stopping layer 62 pattern and the interlayer insulating layer 61. At this time, the thickness of the interlayer insulating layer 63 is of the height of a bottom electrode of a capacitor, so it may be properly controlled.
Referring to FIG. 2C, a capacitor-forming region is defined by selectively etching an interlayer insulating layer 63 of a cell region A, and simultaneously defining a portion to be a metal contact by selectively etching an interlayer insulating layer 63, an etching stopping layer 62, and an interlayer insulating layer 61 of the logic region B.
After depositing materials for bottom electrode of a cell capacitor, such as a tungsten material, the CMP or an entire etching is carried out on a surface of a capacitor insulating layer 63 to form a bottom electrode 64 in a cell region and a plug 64, such as a tungsten material in the logic region B.
Referring to FIG. 2D, after depositing a dielectric layer 65 for a cell capacitor, the dielectric layer 65 remains in the cell region A where a cell capacitor may be formed; in other regions, the dielectric layer is removed using a photo etching process. The dielectric layer 65 is formed using materials such as Ta2O5 and/or BST.
Subsequently, a conductive layer is deposited and a photo-etching process is preferably used to form a capacitor top electrode 66 in the cell region A and wiring 66 is formed in the logic region B.
This second embodiment of a conventional method has more problems than that of the first embodiment of the conventional method, as described above.
First, materials are deposited for top electrode, and a top electrode is formed through blanket etching with proper design, but this method may not be possible in all cases. To form a MIS and/or a MIM cell capacitor and logic wiring at the same time, after depositing a dielectric layer for a cell capacitor, a photo-etching process including a dry etching is carried out. However, a photoresist and a plasma process are adapted in a capacitor dielectric layer, which may have good leakage characteristics, thereby generating deterioration in the characteristics.
Second, a cell storage node is formed when a bottom electrode is simultaneously formed, so it is difficult to fill a storage node with electrodes. This is more serious when a pattern is minimized, and a short circuit between a DRAM cell bit line and a storage node contact may occur.
Third, when a logic analog capacitor is formed by adapting this process, the number of processes is increased and, moreover, because of the topology of an analog capacitor, it is difficult to planarize an interlayer insulating layer.
A method of semiconductor manufacturing is provided, which may operate at high speed and yield in a stable and simple way.
In accordance with one aspect of the disclosure, a method for manufacturing a semiconductor device having a first capacitor in a memory cell region and a second capacitor in a logic region is provided, wherein the method includes the steps of: a) forming an interlayer insulating layer on a blanket substrate; b) simultaneously forming a first opening portion and a second opening portion for the first capacitor and the second capacitor by selectively etching the interlayer insulating layer respectively; c) simultaneously forming bottom electrodes of the first capacitor and the second capacitor, by forming a conductive layer within the first opening portion and the second opening portion; d) forming a dielectric layer on the bottom electrodes of the first capacitor and the second capacitor; and e) forming top electrodes of the first capacitor and the second capacitor on the dielectric layer.
In accordance with another aspect of the disclosure, a method for manufacturing a semiconductor device having a first capacitor in a memory cell region and a second capacitor in a logic region is provided, wherein the method includes the steps of: a) forming a first interlayer insulating layer; b) forming an etching stopping layer on the first interlayer insulating layer in the second capacitor region; c) forming a second interlayer insulating layer covering the first interlayer insulating layer and the etching stopping layer; d) forming a first opening portion for the first capacitor by etching the second interlayer insulating layer of the memory cell region and the first interlayer insulating layer, and at the same time, forming a second opening portion for the second capacitor by etching the second interlayer insulating layer on the etching stopping layer; e) simultaneously forming bottom electrodes of the first capacitor and the second capacitor, by forming a conductive layer within the first opening portion and the second opening portion; f) forming a dielectric layer on the bottom electrodes of the first capacitor and the second capacitor; and g) forming top electrodes of the first capacitor and the second capacitor on the dielectric layer.